A practical performance comparison detailing hand-optimized assembly kernels for ML-KEM polynomial arithmetic on modern x86-64 and ARM64 microarchitectures.
Utilizing 512-bit ZMM registers allows an entire 32-coefficient NTT butterfly stage to be computed in 4 clock cycles using VPADDW, VPSUBW, and VPMULLW instructions. We examine cache prefetching, register allocation to eliminate spills, and pipelining techniques that achieve over 150,000 encapsulations per second per core.
On ARMv8/ARMv9 architectures, 128-bit NEON vector registers process 8 coefficients per instruction. We evaluate the impact of dual-issue vector pipelines, polynomial interleave scheduling, and the elimination of micro-architectural stalls in low-power server environments.
Detailed benchmark results across Intel Xeon Emerald Rapids, AMD EPYC Genoa, and AWS Graviton3 processors, demonstrating that modern vectorized ML-KEM implementations achieve comparable or superior throughput to legacy RSA-3072 and ECDH P-384.